LPC3250FET296/01K | NXP

Single-chip microcontroller, LPC3250FET296/01K, NXP

The LPC3250FET296/01K embedded microcontroller was designed for low-power, high-performance applications. NXP achieved its performance goals using a 90-nanometer process to implement an ARM926EJ-S CPU core with a vector floating-point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3250FET296/01K operates at CPU frequencies of up to 266 MHz. The NXP implementation uses an ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU).

The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware-based set of DSP instruction extensions, which includes single-cycle MAC operations and hardware-based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache, a 32 kB data cache, and 256 kB of on-chip memory.

Features

• External memory controller for DDR and SDR SDRAM as well as for static devices
• WatchDog timer clocked by the peripheral clock
• Standard ARM test/debug interface for compatibility with existing tools
• Stop mode saves power while allowing many peripheral functions to restart CPU activity
• Boundary scan for simplified board testing

Applications

• Consumer
• Medical
• Industrial
• Network control