Synchronous Flow-through Static Ram, IS45S16160J-6BLA1, Integrated Silicon Solution INC
ISSI's 256 Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256 Mb SDRAM is organized as follows. The 256 Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256 Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256 Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
Features
- Internal bank for hiding row access/precharge
- Auto Refresh (CBR)
- Self Refresh
- Random column address every clock cycle
- Burst read/write and burst read/single write operations capability
- Burst termination by burst stop and precharge command
