IS43LR32160C-6BLI | Integrated Silicon Solution INC

Mobile DDR SDRAM, IS43LR32160C-6BLI, Integrated Silicon Solution INC

The IS43LR32160C-6BLI is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Features

• Four internal banks for concurrent operation
• All inputs except data & DM are sampled at the rising edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• Auto & self refresh
• Concurrent Auto Precharge