TLC555CDR | Texas Instruments

CMOS Timer, TLC555CDR, Texas Instruments

The TLC555CDR is a CMOS monolithic timing circuit compatible with CMOS, TTL, and MOS logic, capable of operating at frequencies up to 2 MHz. Its high input impedance allows the use of smaller timing capacitors than those used with the NE555 or LM555, enabling more accurate time delays and oscillations. The device also features low power consumption across its full supply-voltage range. The TLC555CDR operates similarly to the NE555: the trigger level is approximately one-third of the supply voltage, and the threshold level is approximately two-thirds. These levels can be modified via the control voltage (CONT) input. When the trigger input (TRIG) falls below the trigger level, the internal flip-flop sets, and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) exceeds the threshold level, the flip-flop resets, and the output goes low. The reset input (RESET) overrides all other inputs, allowing a new timing cycle to begin. When the output is low, a low-impedance path exists between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

Features

• Capable of operation in astable mode
• CMOS output capable of swinging rail to rail
• High output current capability
• Low supply current reduces spikes during output transitions

Applications

• Precision timing
• Pulse generation
• Sequential timing
• Time delay generation
• Pulse width modulation
• Pulse position modulation
• Linear ramp generator