Binary Counter, SN74LS93D, Texas Instruments
Each monolithic counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-eight for SN74LS93D. To use the maximum count length (decade, divide-by-twelve, or four-bit binary) of the counter, the CKB input is connected to the QA output. The input count pulse is applied to the CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counter by connecting the QD output to the CKA input and applying the input count to the CKB input, which gives a divide-by-ten square wave at output QA.