SN54LS191J | Texas Instruments

Synchronous Up/Down Counter, SN54LS191J, Texas Instruments

The SN54LS191J is a synchronous, reversible up/down counter having a complexity of 58 equivalent gates. The SN54LS191J is a 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low.

A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter counts up, and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry may occur if both the clock and enable are low and the down/up input is high during a load pulse.

Features

• Single Down/Up Count Control Line
• Count Enable Control Input
• Ripple Clock Output for Cascading
• Asynchronously Presettable with Load Control
• Parallel Outputs
• Cascadable for n-Bit Applications