State Bus Synchronous Sram, IS61NLP102436B-200TQLI, Integrated Silicon Solution INC
The 36Meg product features a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, “no-wait-state” device for networking and communications applications. It is organized as 1,048,476 words by 36 bits or 2,096,952 words by 18 bits, fabricated with ISSI’s advanced CMOS technology. Incorporating a “no-wait-state” feature, wait cycles are eliminated when the bus switches from read to write or write to read. This product integrates a 2-bit burst counter, a high-speed SRAM core, and high-drive-capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable (CKE) is HIGH. In this state, the internal device holds its previous values.
Features
- No wait cycles between Read and Write
- Individual Byte Write Control
- Single Read/Write control pin
- Clock controlled, registered address, data and control
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- Common data inputs and data outputs
