State Bus Sram, IS61NLF102436B-6.5TQLI, Integrated Silicon Solution INC
The 36Mb device is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, 'no wait' state memory for networking and communication applications. The device is organized as 1,048,476 words by 36 bits and is fabricated with ISSI’s advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write or write to read. This device integrates a 2-bit burst counter, a high-speed SRAM core, and high-drive-capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable (CKE) is HIGH. In this state, the internal device holds its previous values.
Features
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single Read/Write control pin
- Clock controlled, registered address, data and control
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- Common data inputs and data outputs
