IS61LPS102418B-200TQLI | Integrated Silicon Solution INC

Synchronous Pipelined Single Cycle Deselect Static Ram, IS61LPS102418B-200TQLI, Integrated Silicon Solution INC

The 18Mb device is a high-speed, low-power synchronous static RAM designed to provide burstable, high-performance memory for communication and networking applications. The device is organized as 524,288 words by 36 bits. Fabricated with ISSI’s advanced CMOS technology, it integrates a 2-bit burst counter, a high-speed SRAM core, and high-drive-capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide, as controlled by the write-control inputs.

Features

• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby