IS46QR16256B-083RBLA2 | Integrated Silicon Solution INC

SDRAM, IS46QR16256B-083RBLA2, Integrated Silicon Solution INC

The memory controller initiates the leveling mode of all DRAM by seƫng bit 7 of MR1 to 1. When entering write leveling mode, the DQ pins are in undeĮned driving mode. During write leveling mode, only the DESELECT command is supported, as well as an MRS command to change the Qoī bit (MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). UponĞdžŝƟng write leveling mode, the MRS command performing the exit (MR1[A7] = 0) may also change the other MR1 bits. Because the controller levels one rank at a Ɵme, the output of other ranks must be disabled by seƫng MR1 bit A12 to 1. The controller may assert ODT aŌer tMOD, at which Ɵŵe the DRAM is ready to accept the ODT signal.

Features

• Data Integrity
• DRAM access bandwidth
• Self Refresh Abort
• Fine Granularity Refresh
• Signal Synchronization
• Signal Integrity
• Power Saving and efficiency